4.4   Proposals for optimising the Gate signal

The correlation of the simulated and measured gate signals indicates, that the main percentage of the noise spike is not induced by too long or not good enough shielded gate tracks/cables, but by the parasitic capacitance between Collector and Gate of the IGBT.

Figure 4.22: Capacitance: IRG4PH40UD

Figure 4.22 shows the capacitance of the used IGBTs (IRG4PH40UD). At a voltage V_CE = 0V the capacitance C_gc = 1250pF, at a voltage V_CE > 30V the capacitance C_gc = 0pF.

The in the inductor stored energy keeps the voltage level V_{CE IGBT1} at about 0V until IGBT2 is turned on. Until this time, the capacitance C_{gc IGBT1} has a value of 1250pF and a spike can be induced.

Considering these facts, a gate resistor of a low value would minimise the noise spike on the gate signal. Figure 4.23 shows a simulated noise spike after changing the gate resistors from 30W to 5W. This modification lowers the voltage level of the noise spike from 5.34V to 3V. Logically, a gate resistor of 0W would eliminate the noise spike in the simulation.

This set-up could not be verified due to time constraints of the author's time frame for this thesis.

Also to consider are the shorter rise and fall times of the IGBTs at a lower gate resistor, causing more interference.

Figure 4.23: Simulation data : gate signal, noise spike, V_power_1 = 650V, Ri = 4,9kW, R_gate = 5W

Due to the good correlation of simulation and measurement results the predicted performance in paragraph 3.6.3 is likely to be achieved after solving the problem with the gate signals.

This page is part of a Frameset: Electrodynamic Sculpture: A Thesis by Rafael Bräg.