3.5 Digital Signal GeneratorTo ensure a delay time between the alternated switching of IGBT1 / IGBT3 (Figure 3.14) and IGBT2 / IGBT4 (Figure 3.15), the signal is generated with digital logic. A backfed Schmitt - Trigger (Figure 3.21, IC1A) generates the clock. A four bit counter (Figure 3.21, IC2) combined with a logic circuit generates the output signal. To prevent a fault signal, generated by jitter in the counter, the free gates of the Schmitt - trigger combined with a R - C delay circuit (R6+C3, R5+C2) are used to smooth this problem.
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Figure 3.21: Digital Signal Generator, Schematic Figure 3.22 is the truth table of the logic in circuit Figure 3.21. Qa, Qb, Qc and Qd are the inputs of the counter, X1 and X2 are the outputs of the circuit (at J4).
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Figure 3.22: Digital Signal Generator: Truth table By changing the value of R2, R1 or C1 the frequency of the signal can be controlled. To activate the output - signal, a 5V - logic level voltage has to be applied at J3. Figure 3.23 shows the output signal at a frequency of 4.15kHz, measured with a Hewlett Packard 54645A Oscilloscope. Figure 3.24 shows the output signal at a frequency of 16kHz. Channel 1 controls IGBT1 and IGBT3, channel 2 controls IGBT2 and IGBT4. Between the alternating switching of the channels is a delay time of 2T/32 or 3T/32. The length of the delay time can be set at J2.
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Figure 3.23: Output signals at 4.15kHz |
Figure 3.24: Output signals at 16kHz |
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The printed circuit board designed, built and tested is shown in Figure 3.25.
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Figure3.25: Digital Signal Generator: PCB, Photo |
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This page is part of a Frameset: Electrodynamic Sculpture: A Thesis by Rafael Bräg. |
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